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AD7328
Rev. A | Page 16 of 36
CAPACITIVE
DAC
CONTROL
LOGIC
COMPARATOR
AGND
SW2
SW1
A
B
C
S
V
IN
0
0
Figure 24. ADC Conversion Phase (Single-Ended)
Figure 25 shows the differential configuration during the ac-
quisition phase. For the conversion phase, SW3 opens and SW1
and SW2 move to Position B (see Figure 26). The output
impedances of the source driving the V
IN
+ and V
IN
pins must
match; otherwise, the two inputs have different settling times,
resulting in errors.
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
SW2
A
A
B
C
S
C
S
V
IN
+
B
V
IN
–
V
REF
0
Figure 25. ADC Differential Configuration During Acquisition Phase
CAPACITIVE
DAC
CONTROL
LOGIC
CAPACITIVE
DAC
COMPARATOR
SW3
SW1
SW2
A
A
B
C
S
C
S
V
IN
+
B
V
IN
–
V
REF
0
Figure 26. ADC Differential Configuration During Conversion Phase
Output Coding
The AD7328 default output coding is set to twos complement.
The output coding is controlled by the coding bit in the control
register. To change the output coding to straight binary coding,
the coding bit in the control register must be set. When operating
in sequence mode, the output coding for each channel in the
sequence is the value written to the coding bit during the last
write to the control register.
Transfer Functions
The designed code transitions occur at successive integer
LSB values (that is, 1 LSB, 2 LSB, and so on). The LSB size
is dependent on the analog input range selected.
Table 7. LSB Sizes for Each Analog Input Range
Input Range
Full-Scale Range/8192 Codes
±10 V
20 V
±5 V
10 V
±2.5 V
5 V
0 V to +10 V
10 V
LSB Size
2.441 mV
1.22 mV
0.61 mV
1.22 mV
The ideal transfer characteristic for the AD7328 when twos
complement coding is selected is shown in Figure 27. The ideal
transfer characteristic for the AD7328 when straight binary coding
is selected is shown in Figure 28.
011...111
011...110
000...001
000...000
111...111
–AGND + 1LSB
+FSR/2 – 1LSB UNIPOLAR RANGE
ANALOG INPUT
AGND – 1LSB
A
100...010
100...001
100...000
0
Figure 27. Twos Complement Transfer Characteristic (Bipolar Ranges)
111...111
111...110
111...000
011...111
AGND + 1LSB
+FSR/2 – 1LSB UNIPOLAR RANGE
ANALOG INPUT
A
000...010
000...001
000...000
0
Figure 28. Straight Binary Transfer Characteristic (Bipolar Ranges)
ANALOG INPUT STRUCTURE
The analog inputs of the AD7328 can be configured as single-
ended, true differential, or pseudo differential via the control
register mode bits (see Table 10). The AD7328 can accept true
bipolar input signals. On power-up, the analog inputs operate as
eight single-ended analog input channels. If true differential or
pseudo differential is required, a write to the control register is
necessary after power-up to change this configuration.
Figure 29 shows the equivalent analog input circuit of the
AD7328 in single-ended mode. Figure 30 shows the equivalent
analog input structure in differential mode. The two diodes
provide ESD protection for the analog inputs.
D
D
V
DD
C2
R1
V
IN
0
V
SS
C1
0
Figure 29. Equivalent Analog Input Circuit (Single-Ended)
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